On-Line Integrity Monitoring of Microprocessor Control Logic

Traditionally, the control logic of most microprocessors is not checked for soft errors due to great overheads while the remaining parts such as memory array and data path are often protected with error correcting codes. This paper presents a low-cost reliability enhancement scheme for the processors’ control logic. We classify control signals into static and dynamic control depending on their changeability for a given instruction, and employ different mechanisms. For static control, signals used in each pipeline stage are integrated into a signature and verified with a cached check code at commit time. The concept of caching signatures is introduced. Dynamic control is examined on the spot in which the signals are created using parity or component-level duplication. Fault injection simulations on an RTL model of a MIPS-like processor demonstrate that our scheme can achieve more than 99% coverage on average with a very small addition of hardware. We have also investigated the criticalness of errors in the processor logic that suggests a direction in devising efficient allocation of redundancy.